Exemplary embodiments relate to the column address counter circuit of a semiconductor memory device and, more particularly, to the column address counter circuit of a semiconductor memory device for a high-speed operation.
There is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require a refresh function of rewriting data at specific intervals.
The nonvolatile memory device receives an address, a command signal, and data at the same time when it receives external data. This operation is based on a characteristic of the nonvolatile memory device, where it sequentially receives or outputs data.
Accordingly, the nonvolatile memory device increases only a start column address whenever an internal clock CK4CNT is toggled.
FIG. 1 is a waveform illustrating data I/O timings of a known semiconductor memory device.
Referring to FIG. 1, in the semiconductor memory device, in a data I/O operation, I/O data is inputted and outputted in synchronization with the rising and falling edges of a data strobe signal DQS which is generated using a clock CLK. That is, whenever the I/O data is inputted or outputted, it is inputted/outputted as a pair at the rising edge and the falling edge of the data strobe signal DQS.
In order to increase the operating speed, in the data I/O operation of the nonvolatile memory device, the clock is internally divided into a rising clock and a falling clock, and data inputted/outputted at the rising edge of the clock are inputted/outputted through data lines that are different from data lines used for inputting/outputting data at the falling edge of the clock.
Furthermore, data inputted and outputted at a rising edge and a falling edge is defined as a pair, and thus a column address always consists of even and odd addresses, such as 0/1, 2/3, 4/5, etc. According to an example, the even column address is allocated to data synchronized with the rising edge, and the odd column address is allocated to data synchronized with the falling edge.
Accordingly, a column address counter does not count all addresses at the rising and falling edges and performs the address count operation, for example, only at the rising edge and then internally allocates even and odd column addresses to data synchronized with the rising edge and the falling edge. Here, the address count operation is performed for only half of the inputted and outputted data, a proper margin for the speed of counting can be secured.
FIGS. 2A and 2B show waveforms of signals illustrating a column address count operation in a known data I/O operation.
Referring to FIG. 2A, in the case where the cycle of a count clock CK4CNT is long, when a count operation is performed based on initial start addresses with a current column address being ‘0’ and a next column address being ‘2’, a column counter performs the count operation at the falling edge (1-1) of the count clock CK4CNT and outputs a current column address. Furthermore, at an edge (2-1), the column counter outputs a next column address as a counted column address.
The column counter directly outputs a column address without a count operation up to a second column address because it has previously counted a current column address and a next column address before the count operation is started. Thereafter, the column counter counts the falling edge of the count clock CK4CNT at edge (3-1) and outputs a column address. In the case where the cycle of the count clock CK4CNT is long, the count operation of the column address can sufficiently secure an adequate margin for the count operation.
Referring to FIG. 2B, in the case where the cycle of the count clock CK4CNT is short, the column counter performs a count operation at the falling edge (1-2) of the count clock CK4CNT and outputs a current column address. At edge (2-2), the column counter outputs a next column address as a counted column address. However, at edge (3-2) where a column address counted by the count operation is outputted, a point of time at which the count operation is finished passes the falling edge of the count clock CK4CNT because the cycle of the count clock CK4CNT is short. In this case, the column address is not properly counted.